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d a t a sh eet product speci?cation supersedes data of 1998 may 20 2004 mar 30 integrated circuits 74lvc161 presettable synchronous 4-bit binary counter; asynchronous reset
2004 mar 30 2 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 features 5 v tolerant inputs for interfacing with 5 v logic wide supply voltage range from 1.2 v to 3.6 v cmos low power consumption direct interface with ttl levels inputs accept voltages up to 5.5 v complies with jedec standard no. jesd8b/jesd36 asynchronous reset synchronous counting and loading two count enable inputs for n-bit cascading positive edge-triggered clock esd protection: C hbm eia/jesd22-a114-b exceeds 2000 v C mm eia/jesd22-a115-a exceeds 200 v. specified from - 40 c to +85 c and - 40 c to +125 c. description the 74lvc161 is a high-performance, low-power, low-voltage, si-gate cmos device and superior to most advanced cmos compatible ttl families. the 74lvc161 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin cp). the outputs (pins q0 to q3) of the counters may be preset to a high-level or a low-level. a low-level at the parallel enable input (pin pe) disables the counting action and causes the data at the data inputs (pins d0 to d3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for pe are met). preset takes place regardless of the levels at count enable inputs (pins cep and cet). a low-level at the master reset input (pin mr) sets all four outputs of the flip-flops (pins q0 to q3) to low-level regardless of the levels at input pins cp, pe, cet and cep (thus providing an asynchronous clear function). the look-ahead carry simplifies serial cascading of the counters. both count enable inputs (pins cep and cet) must be high to count. the cet input is fed forward to enable the terminal count output (pin tc). the tc output thus enabled will produce a high output pulse of a duration approximately equal to a high-level output of q0. this pulse can be used to enable the next cascaded stage. the maximum clock frequency for the cascaded counters is determined by t phl (propagation delay cp to tc) and t su (set-up time cep to cp) according to the following formula: f max 1 t phl max () t su + ------------------------------------ - =
2004 mar 30 3 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc . ordering information symbol parameter conditions typical unit t phl /t plh propagation delay c l = 50 pf; v cc = 3.3 v cp to qn 3.9 ns cp to tc 4.5 ns mr to qn 3.5 ns mr to tc 4.7 ns cet to tc 3.3 ns f clk(max) maximum clock frequency 200 mhz c i input capacitance 5.0 pf c pd power dissipation capacitance per gate notes 1 and 2 18 pf type number temperature range pins package material code 74lvc161d - 40 c to +125 c 16 so16 plastic sot109-1 74lvc161db - 40 c to +125 c 16 ssop16 plastic sot338-1 74lvc161pw - 40 c to +125 c 16 tssop16 plastic sot403-1 74LVC161BQ - 40 c to +125 c 16 dhvqfn16 plastic sot763-1
2004 mar 30 4 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 function table see note 1. note 1. * = the tc output is high when cet is high and the counter is at terminal count (hhhh). h = high voltage level. h = high voltage level one set-up time prior to the low-to-high clock transition. l = low voltage level. l = low voltage level one set-up time prior to the low-to-high clock transition. q = lower case letters indicate the state of the referenced output one set-up time prior to the low-to-high clock transition. x = dont care. -= low-to-high clock transition. pinning operating modes input output mr cp cep cet pe dn qn tc reset (clear) l xxxxxl l parallel load h - xx l l l l h - xx l hh * count h - h h h x count * hold (do nothing) hxlxhxq n * hxx l hxq n l pin symbol description 1 mr synchronous master reset (active low) 2 cp clock input (low-to-high, edge-triggered) 3 d0 data input 4 d1 data input 5 d2 data input 6 d3 data input 7 cep count enable inputs 8 gnd ground (0 v) 9 pe parallel enable input (active low) 10 cet count enable carry input 11 q3 ?ip-?op output 12 q2 ?ip-?op output 13 q1 ?ip-?op output 14 q0 ?ip-?op output 15 tc terminal count output 16 v cc supply voltage
2004 mar 30 5 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 fig.1 pin configuration so16 and (t)ssop16. handbook, halfpage mr cp 161 d0 d1 d2 d3 cep gnd v cc tc q0 q1 q3 cet q2 pe 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 mna904 fig.2 pin configuration dhvqfn16. handbook, halfpage 116 gnd (1) mr v cc 8 2 3 4 5 7 cp d0 d1 d2 d3 15 14 13 12 10 611 9 gnd top view mna980 cep pe cet q3 q2 q1 q0 tc (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. handbook, halfpage mna905 q0 q1 cp q2 q3 tc 3 4 2 5 6 9 14 13 15 12 11 mr 1 cep 7 cet 10 d0 d1 d2 d3 pe fig.3 logic symbol. handbook, halfpage mna906 15 11 12 3 4 5 6 14 13 7 10 g3 1 r 9 m1 g4 2 c2 / 1,3,4 + 1,2d 4 ct = 15 ctr4 fig.4 logic symbol (ieee/iec).
2004 mar 30 6 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 handbook, halfpage mna907 parallel load circuitry binary counter cep tc 15 cet pe cp mr q0 q1 q2 q3 d0 d1 d2 d3 14 13 12 11 3456 7 10 9 2 1 fig.5 functional diagram. handbook, halfpage mna908 0 15 14 13 12 1 2 3 4 5 6 7 11 10 9 8 fig.6 state diagram. handbook, full pagewidth mna909 cp pe tc mr inhibit count cep cet d0 d2 d1 d3 q0 q2 q1 q3 reset preset 12 13 14 15 0 1 2 fig.7 timing sequence. typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and tw o; inhibit.
2004 mar 30 7 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 handbook, full pagewidth mna910 q3 tc q2 q1 q0 d ff0 q cp pe cep cet d0 d1 d2 d3 cp mr d ff1 q cp d ff2 q cp d ff3 r d r d r d r d q cp q q q q fig.8 logic diagram.
2004 mar 30 8 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v); note 1. notes 1. stresses beyond those listed may cause permanent damage to the device. these are stress rating only and functional operation of the device at these or any other condition beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. for so16 packages: above 70 c derate linearly with 8 mw/k. for ssop16 and tssop16 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn16 packages: above 60 c derate linearly with 4.5 mw/k. symbol parameter conditions min. max. unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage 0 v cc v t amb operating temperature in free-air - 40 +125 c t r ,t f input rise and fall times v cc = 1.2 v to 2.7 v 0 20 ns/v v cc = 2.7 v to 3.6 v 0 10 ns/v symbol parameter conditions min. typ. max. unit v cc supply voltage - 0.5 - +6.5 v i ik input diode current v i <0v -- 50 - ma v i input voltage note 2 - 0.5 - +6.5 v i ok output diode current v o >v cc or v o <0v - 50 - ma v o output voltage note 2 - 0.5 - v cc + 0.5 v i o output source of sink current v o =0vtov cc - 50 - ma i cc ,i gnd v cc or gnd current - 100 - ma t stg storage temperature - 65 - +150 c p tot power dissipation t amb = - 40 c to +125 c; note 3 - 500 - mw
2004 mar 30 9 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 dc characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter test conditions min. typ. (1) max. unit other v cc (v) t amb = - 40 c to +85 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 2.7 to 3.6 v cc - 0.2 v cc - v i o = - 12 ma 2.7 v cc - 0.5 -- v i o = - 18 ma 3.0 v cc - 0.6 -- v i o = - 24 ma 3.0 v cc - 0.8 -- v v ol low-level output voltage v i =v ih or v il i o = 100 m a 2.7 to 3.6 - gnd 0.2 v i o =12ma 2.7 -- 0.4 v i o =24ma 3.0 -- 0.55 v i li input leakage current v i = 5.5 v or gnd 3.6 - 0.1 5 m a i cc quiescent supply current v i =v cc or gnd; i o =0a 3.6 - 0.1 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0a 2.7 to 3.6 - 5 500 m a
2004 mar 30 10 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 note 1. typical values are measured at v cc = 3.3 v and t amb =25 c. t amb = - 40 c to +125 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 2.7 to 3.6 v cc - 0.3 -- v i o = - 12 ma 2.7 v cc - 0.65 -- v i o = - 18 ma 3.0 v cc - 0.75 -- v i o = - 24 ma 3.0 v cc - 1 -- v v ol low-level output voltage v i =v ih or v il i o = 100 m a 2.7 to 3.6 -- 0.3 v i o =12ma 2.7 -- 0.6 v i o =24ma 3.0 -- 0.8 v i li input leakage current v i = 5.5 v or gnd 3.6 -- 20 m a i cc quiescent supply current v i =v cc or gnd; i o =0a 3.6 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0a 2.7 to 3.6 -- 5000 m a symbol parameter test conditions min. typ. (1) max. unit other v cc (v)
2004 mar 30 11 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 ac characteristics gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w . symbol parameter conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 c to +85 c ; note 1 t phl /t plh propagation delay cp to qn see figs 9 and 14 1.2 - 17 - ns 2.7 1.5 - 7.2 ns 3.0 to 3.6 1.5 3.9 (2) 7.3 ns propagation delay cp to tc see figs 9 and 14 1.2 - 20 - ns 2.7 1.5 - 7.8 ns 3.0 to 3.6 1.5 4.5 (2) 7.8 ns propagation delay cet to tc see figs 10 and 14 1.2 - 16 - ns 2.7 1.5 - 6.5 ns 3.0 to 3.6 1.5 3.3 (2) 6.0 ns t phl propagation delay mr to qn see figs 11 and 14 1.2 - 17 - ns 2.7 1.5 - 7.1 ns 3.0 to 3.6 1.5 3.5 (2) 6.4 ns propagation delay mr to tc see figs 11 and 14 1.2 - 18 - ns 2.7 1.5 - 8.6 ns 3.0 to 3.6 1.5 4.7 (2) 8.0 ns t w clock pulse width high or low see fig.9 2.7 5.0 -- ns 3.0 to 3.6 4.0 1.2 (2) - ns master reset width low see fig.11 2.7 4.0 -- ns 3.0 to 3.6 3.0 1.6 (2) - ns t rem removal time mr to cp see fig.11 2.7 0.0 -- ns 3.0 to 3.6 0.5 0.0 (2) - ns t su set-up time dn to cp see fig.12 2.7 3.0 -- ns 3.0 to 3.6 2.5 1.0 (2) - ns set-up time pe to cp see fig.12 2.7 3.5 -- ns 3.0 to 3.6 3.0 1.2 (2) - ns set-up time cep, cet to cp see fig.13 2.7 5.5 -- ns 3.0 to 3.6 5.0 2.1 (2) - ns t h hold time dn, pe, cep, cet to cp see figs 12 and 13 2.7 0.0 -- ns 3.0 to 3.6 0.5 0.0 (2) - ns f clk(max) maximum clock frequency see fig.9 2.7 150 -- mhz 3.0 to 3.6 150 200 (2) - mhz t sk(0) skew note 3 3.0 to 3.6 -- 1.0 ns
2004 mar 30 12 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 notes 1. all typical values are measured at t amb =25 c. 2. typical values are measured at v cc = 3.3 v. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. t amb = - 40 c to +125 c t phl /t plh propagation delay cp to qn see figs 9 and 14 1.2 --- ns 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 9.5 ns propagation delay cp to tc see figs 9 and 14 1.2 --- ns 2.7 1.5 - 10.0 ns 3.0 to 3.6 1.5 - 10.0 ns propagation delay cet to tc see figs 10 and 14 1.2 --- ns 2.7 1.5 - 8.5 ns 3.0 to 3.6 1.5 - 7.5 ns t phl propagation delay mr to qn see figs 11 and 14 1.2 --- ns 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 8.0 ns propagation delay mr to tc see figs 11 and 14 1.2 --- ns 2.7 1.5 - 11.0 ns 3.0 to 3.6 1.5 - 10.0 ns t w clock pulse width high or low see fig.9 2.7 5.0 -- ns 3.0 to 3.6 4.0 -- ns master reset width low see fig.11 2.7 4.0 -- ns 3.0 to 3.6 3.0 -- ns t rem removal time mr to cp see fig.11 2.7 0.0 -- ns 3.0 to 3.6 0.5 -- ns t su set-up time dn to cp see fig.12 2.7 3.0 -- ns 3.0 to 3.6 2.5 -- ns set-up time pe to cp see fig.12 2.7 3.5 -- ns 3.0 to 3.6 3.0 -- ns set-up time cep, cet to cp see fig.13 2.7 5.5 -- ns 3.0 to 3.6 5.0 -- ns t h hold time dn, pe, cep, cet to cp see figs 12 and 13 2.7 0.0 -- ns 3.0 to 3.6 0.5 -- ns f clk(max) maximum clock frequency see fig.9 2.7 150 -- mhz 3.0 to 3.6 150 -- mhz t sk(0) skew note 3 3.0 to 3.6 -- 1.5 ns symbol parameter conditions min. typ. max. unit waveforms v cc (v)
2004 mar 30 13 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 ac waveforms handbook, full pagewidth mna911 cp input qn, tc output t phl t plh t w 1/f max v m v oh v i gnd v ol v m fig.9 clock (cp) to outputs (qn, tc) propagation delays, the clock pulse width and the maximum clock frequency. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are typical output voltage drop that occur with the output load. handbook, halfpage mna912 t phl t plh v m v m tc output cet input gnd v i v oh v ol v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are typical output voltage drop that occur with the output load. fig.10 input (cet) to output (tc) propagation delays.
2004 mar 30 14 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 handbook, full pagewidth mna913 mr input cp input qn, tc output t phl t w t rem v m v oh v i v i gnd gnd v ol v m v m fig.11 master reset ( mr) pulse width, the master reset to output (qn, tc) propagation delays and the master reset to clock (cp) removal times. handbook, full pagewidth mna914 gnd gnd gnd t h t h t su t su t su t h t h t su v m v m v m v i v i cp input pe input dn input v i fig.12 set-up and hold times for the input (dn) and parallel enable input ( pe). the shaded areas indicate when the input is permitted to change for predictable output performance.
2004 mar 30 15 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 handbook, full pagewidth mna915 t h t su t h t su gnd v i v m v m gnd v i cp input cep, cet input fig.13 cep and cet set-up and hold times. the shaded areas indicate when the input is permitted to change for predictable output performance. v ext v cc v i v o mna616 d.u.t. c l r t r l r l pulse generator fig.14 load circuitry for switching times. definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. note 1. the circuit performs better when r l = 1000 w . v cc v i c l r l v ext t plh /t phl t pzh /t phz t pzl /t plz 1.2 v v cc 50 pf 500 w (1) open gnd 2 v cc 2.7 v 2.7 v 50 pf 500 w open gnd 2 v cc 3.0 v to 3.6 v 2.7 v 50 pf 500 w open gnd 2 v cc
2004 mar 30 16 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 package outlines x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
2004 mar 30 17 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 8 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot338-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 8 16 9 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 a max. 2
2004 mar 30 18 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
2004 mar 30 19 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.6 3.4 d h 2.15 1.85 y 1 2.6 2.4 1.15 0.85 e 1 2.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot763-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot763-1 dhvqfn16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 27 15 10 9 8 1 16 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
2004 mar 30 20 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74lvc161 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r20/03/pp 21 date of release: 2004 mar 30 document order number: 9397 750 10505

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